1. Field of the Invention
The present invention relates to a class AB operational amplifier and output stage quiescent current control method, and more particularly, to a class AB operational amplifier and output stage quiescent current control method capable of reducing variation of an output stage quiescent current due to process variation and bias variation.
2. Description of the Prior Art
An output stage quiescent current relates to an output stage current when no signal is inputted into an operational amplifier, and is generally maintained within a stable range to meet system requirements. In the prior art, the output stage quiescent current is generally maintained at a specific multiple of a bias current by negative feedback.
Please reference FIG. 1, which is a schematic diagram of a class AB operational amplifier 10 in the prior art. The class AB operational amplifier 10 includes input terminals Vin−, Vin+, transistors M1, M2, a current source 102 and a comparator 104. In short, since input voltages of the comparator 104 are a gate voltage Vg1 of the transistor M1 and a gate voltage Vg2 of the transistor M2, and sources of both the transistors M1, M2 are connected to a system voltage VDD, the comparator 104 can perform negative feedback to make a gate-to-source voltage Vgs1 of the transistor M1 equal to a gate-to-source voltage Vgs2 of the transistor M2. As a result, when no signal is inputted into the input terminals Vin−, Vin+, a ratio of an output stage quiescent current IQ to a bias current Id2 supplied by the current source 102 is substantially equal to a ratio of a W/L ratio (W/L)1 of the transistor M1 to a W/L ratio (W/L)2 of the transistor M2.
In detail, a current Id of a transistor is generally denoted as follows:
                              Id          =                                    1              2                        ⁢                          μ              n                        ⁢            Cox            ⁢                          W              L                        ⁢                                          (                                  Vgs                  -                                      V                    T                                                  )                            2                        ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                  Vds                                            )                                      ,                            (                  Eq          .                                          ⁢          1                )            
where λ is a process variation parameter for denoting a channel length modulation effect, i.e. when a drain-to-source voltage is higher than a saturation voltage, an effective length of the transistor is shorter than an actual length L, such that the current Id is increased.
Then, Eq. 1 can be rewritten as follows:
                              Vgs          =                                    V              T                        +                                                            2                  ⁢                  Id                                                                      μ                    n                                    ⁢                  Cox                  ⁢                                      W                    L                                    ⁢                                      (                                          1                      +                                              λ                        ⁢                                                                                                  ⁢                        Vds                                                              )                                                                                      ,                            (                  Eq          .                                          ⁢          2                )            
Since the gate-to-source voltage Vgs1 is equal to the gate-to-source voltage Vgs2, a relation between the output stage quiescent current IQ and the bias current Id2 can be denoted as follows:
                                                        IQ                                                                    (                                          W                      L                                        )                                    1                                ⁢                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      1                                                        )                                                              =                                                    Id                ⁢                                                                  ⁢                2                                                                                  (                                          W                      L                                        )                                    2                                ⁢                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      2                                                        )                                                                    ,                            (                  Eq          .                                          ⁢          3                )            
Since the gate voltage Vg2 is equal to a source voltage Vd2 in the transistor M2, Eq. 3 can be rewritten as follows:
                              IQ          =                                                                                                                (                                              W                        L                                            )                                        1                                    ⁢                                      (                                          1                      +                                              λ                        ⁢                                                                                                  ⁢                        Vds                        ⁢                                                                                                  ⁢                        1                                                              )                                                                                                              (                                              W                        L                                            )                                        2                                    ⁢                                      (                                          1                      +                                              λ                        ⁢                                                                                                  ⁢                        Vds                        ⁢                                                                                                  ⁢                        2                                                              )                                                              ⁢              Id              ⁢                                                          ⁢              2                        =                                                                                (                                          W                      L                                        )                                    1                                                                      (                                          W                      L                                        )                                    2                                            ⁢                                                (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      1                                                        )                                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vgs                      ⁢                                                                                          ⁢                      2                                                        )                                            ⁢              Id              ⁢                                                          ⁢              2                                      ,                            (                  Eq          .                                          ⁢          4                )            
However, since a source voltage Vd1 of the transistor M1, i.e. an output voltage, is half the system voltage VDD when no signal is inputted into the input terminals Vin−, Vin+, a drain-to-source voltage Vds1 of the transistor M1 is also half the system voltage VDD, i.e. about 2.5V, while the gate-to-source voltage Vgs2 is generally about 0.8V. As a result, as can be seen from Eq. 4, when the system voltage VDD rises, the drain-to-source voltage Vds1 rises as well, while the gate-to-source voltage Vgs2 remains unchanged, such that the output stage quiescent current IQ is increased. In addition, both the gate-to-source voltage Vgs2 and the process variation parameter λ vary with process variation. Thus, the output stage quiescent current IQ becomes greater when both the gate-to-source voltage Vgs2 and the process variation parameter λ become smaller, while the output stage quiescent current IQ becomes smaller when both the gate-to-source voltage Vgs2 and the process variation parameter λ become greater. In other words, the class AB operational amplifiers 10 under the same process conditions have wider distribution of the output stage quiescent currents IQ, i.e. statistically larger standard deviation.
As can be seen from the above, in the prior art, the ratio of the output stage quiescent current IQ to the bias current Id2 is not purely equal to the ratio of the W/L ratio (W/L)1 to the W/L ratio (W/L)2, and varies with process variation and the system voltage VDD as well, i.e. channel length modulation effect, such that the output stage quiescent current IQ cannot be maintained within the stable range. Thus, there is a need for improvement in the prior art.